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IF((V(In_2A)>3.5 && V(In_2B)<1.5) || (V(In_2A)<1.5 && V(In_2B)>3.5), 5, 0) } * Gate 3 EXOR3 Out_3 0 VALUE = { IF((V(In_3A)>3.5 && V(In_3B)<1.5) || (V(In_3A)<1.5 && V(In_3B)>3.5), 5, 0) } * Gate 4 EXOR4 Out_4 0 VALUE = { IF((V(In_4A)>3.5 && V(In_4B)<1.5) || (V(In_4A)<1.5 && V(In_4B)>3.5), 5, 0) } .ENDS 74HC86 ","description":"Quad 2-input XOR","public":true,"user_id":200061,"created_at":"2025-05-19T16:56:09.230Z","updated_at":"2025-05-19T17:15:04.175Z","official":false},{"id":132,"name":"74HC02","vertical_pins":7,"horizontal_pins":0,"pin_labels":{"right-0":"Vcc","right-1":"In_4B","right-2":"In_4A","right-3":"Out_4","right-4":"In_3B","right-5":"In_3A","right-6":"Out_3","left-0":"Gnd","left-1":"Out_2","left-2":"In_2B","left-3":"In_2A","left-4":"Out_1","left-5":"In_1B","left-6":"In_1A","initial_checked":["right-0","right-1","right-2","right-3","right-4","right-5","right-6","left-0","left-1","left-2","left-3","left-4","left-5","left-6"]},"netlist":".subckt 74HC02 In_1A In_1B Out_1 In_2A In_2B Out_2 Gnd Out_3 In_3A In_3B Out_4 In_4A In_4B Vcc * 74HC02 Quad 2-Input NOR Gate Behavioral Model * Inputs: In_xA, In_xB (logic inputs) * Outputs: Out_x (logic output) * Power: Vcc (logic HIGH = 5V), Gnd (logic LOW = 0V) .SUBCKT 74HC02 In_1A In_1B Out_1 In_2A In_2B Out_2 GND Out_3 In_3A In_3B Out_4 In_4A In_4B VCC * Gate 1 ENOR1 Out_1 0 VALUE = { IF(V(In_1A)<1.5 && V(In_1B)<1.5, 5, 0) } * Gate 2 ENOR2 Out_2 0 VALUE = { IF(V(In_2A)<1.5 && V(In_2B)<1.5, 5, 0) } * Gate 3 ENOR3 Out_3 0 VALUE = { IF(V(In_3A)<1.5 && V(In_3B)<1.5, 5, 0) } * Gate 4 ENOR4 Out_4 0 VALUE = { IF(V(In_4A)<1.5 && V(In_4B)<1.5, 5, 0) } .ENDS 74HC02 ","description":"Quad 2-input NOR","public":true,"user_id":200061,"created_at":"2025-05-19T16:55:37.090Z","updated_at":"2025-05-19T17:17:01.934Z","official":false},{"id":110,"name":"74HC32","vertical_pins":7,"horizontal_pins":0,"pin_labels":{"right-0":"Vcc","right-1":"In_4B","right-2":"In_4A","right-3":"Out_4","right-4":"In_3B","right-5":"In_3A","right-6":"Out_3","left-0":"Gnd","left-1":"Out_2","left-2":"In_2B","left-3":"In_2A","left-4":"Out_1","left-5":"In_1B","left-6":"In_1A","initial_checked":["right-0","right-1","right-2","right-3","right-4","right-5","right-6","left-0","left-1","left-2","left-3","left-4","left-5","left-6"]},"netlist":".subckt 74HC32 In_1A In_1B Out_1 In_2A In_2B Out_2 Gnd Out_3 In_3A In_3B Out_4 In_4A In_4B Vcc * 74HC32 Quad 2-Input OR Gate Behavioral Model * Inputs: In_xA, In_xB * Outputs: Out_x * Power: Vcc (logic HIGH = 5V), Gnd (logic LOW = 0V) .SUBCKT 74HC32 In_1A In_1B Out_1 In_2A In_2B Out_2 GND Out_3 In_3A In_3B Out_4 In_4A In_4B VCC * Gate 1 E1 Out_1 0 VALUE = { IF(V(In_1A)>1.5 || V(In_1B)>1.5, 5, 0) } * Gate 2 E2 Out_2 0 VALUE = { IF(V(In_2A)>1.5 || V(In_2B)>1.5, 5, 0) } * Gate 3 E3 Out_3 0 VALUE = { IF(V(In_3A)>1.5 || V(In_3B)>1.5, 5, 0) } * Gate 4 E4 Out_4 0 VALUE = { IF(V(In_4A)>1.5 || V(In_4B)>1.5, 5, 0) } .ENDS 74HC32 ","description":"Quad 2-input OR","public":true,"user_id":200061,"created_at":"2025-05-12T20:19:19.800Z","updated_at":"2025-05-19T17:18:13.950Z","official":false},{"id":109,"name":"74HC08","vertical_pins":7,"horizontal_pins":0,"pin_labels":{"right-0":"Vcc","right-1":"In_4B","right-2":"In_4A","right-3":"Out_4","right-4":"In_3B","right-5":"In_3A","right-6":"Out_3","left-0":"Gnd","left-1":"Out_2","left-2":"In_2B","left-3":"In_2A","left-4":"Out_1","left-5":"In_1B","left-6":"In_1A","initial_checked":[]},"netlist":".subckt 74HC08 In_1A In_1B Out_1 In_2A In_2B Out_2 Gnd Out_3 In_3A In_3B Out_4 In_4A In_4B Vcc * 74HC08 Quad 2-Input AND Gate Behavioral Model * Inputs: In_xA, In_xB * Outputs: Out_x * Power: Vcc (logic HIGH = 5V), Gnd (logic LOW = 0V) .SUBCKT 74HC08 In_1A In_1B Out_1 In_2A In_2B Out_2 GND Out_3 In_3A In_3B Out_4 In_4A In_4B VCC * Gate 1 E1 Out_1 0 VALUE = { IF(V(In_1A)>1.5 && V(In_1B)>1.5, 5, 0) } * Gate 2 E2 Out_2 0 VALUE = { IF(V(In_2A)>1.5 && V(In_2B)>1.5, 5, 0) } * Gate 3 E3 Out_3 0 VALUE = { IF(V(In_3A)>1.5 && V(In_3B)>1.5, 5, 0) } * Gate 4 E4 Out_4 0 VALUE = { IF(V(In_4A)>1.5 && V(In_4B)>1.5, 5, 0) } .ENDS 74HC08 ","description":"Quad 2-input AND","public":true,"user_id":200061,"created_at":"2025-05-12T20:14:24.416Z","updated_at":"2025-05-19T20:18:11.018Z","official":false},{"id":54,"name":"74HC00","vertical_pins":7,"horizontal_pins":0,"pin_labels":{"right-0":"Vcc","right-1":"In_4B","right-2":"In_4A","right-3":"Out_4","right-4":"In_3B","right-5":"In_3A","right-6":"Out_3","left-0":"Gnd","left-1":"Out_2","left-2":"In_2B","left-3":"In_2A","left-4":"Out_1","left-5":"In_1B","left-6":"In_1A","initial_checked":["right-0","right-1","right-2","right-3","right-4","right-5","right-6","left-0","left-1","left-2","left-3","left-4","left-5","left-6"]},"netlist":".subckt 74HC00 In_1A In_1B Out_1 In_2A In_2B Out_2 Gnd Out_3 In_3A In_3B Out_4 In_4A In_4B Vcc * 74HC00 Quad 2-Input NAND Gate Behavioral Model * Inputs: In_xA, In_xB * Outputs: Out_x * Power: Vcc (logic HIGH = 5V), Gnd (logic LOW = 0V) .SUBCKT 74HC00 In_1A In_1B Out_1 In_2A In_2B Out_2 GND Out_3 In_3A In_3B Out_4 In_4A In_4B VCC * Gate 1 EN1 Out_1 0 VALUE = { IF(V(In_1A)>1.5 && V(In_1B)>1.5, 0, 5) } * Gate 2 EN2 Out_2 0 VALUE = { IF(V(In_2A)>1.5 && V(In_2B)>1.5, 0, 5) } * Gate 3 EN3 Out_3 0 VALUE = { IF(V(In_3A)>1.5 && V(In_3B)>1.5, 0, 5) } * Gate 4 EN4 Out_4 0 VALUE = { IF(V(In_4A)>1.5 && V(In_4B)>1.5, 0, 5) } .ENDS 74HC00 ","description":"Quad 2-input NAND","public":true,"user_id":200061,"created_at":"2025-04-16T17:34:31.881Z","updated_at":"2025-05-19T17:19:37.969Z","official":false}],"official_ics":[{"id":1393,"name":"LM358","vertical_pins":4,"horizontal_pins":0,"pin_labels":{"left-3":"OUT1","left-2":"IN1-","left-1":"IN1+","left-0":"GND","right-3":"IN2+","right-2":"IN2-","right-1":"OUT2","right-0":"VCC","initial_checked":[]},"netlist":".subckt LM358 OUT1 IN1- IN1+ GND IN2+ IN2- OUT2 VCC * Dual single-supply op-amp macromodel. GBW ~1MHz, output swings to GND and ~VCC-1.5V. * Pin order is DIP-8 pin 1..8 X1 IN1+ IN1- VCC GND OUT1 lm358_amp X2 IN2+ IN2- VCC GND OUT2 lm358_amp * every pin has a 1 Gohm path to ground, so a chip placed on the board before it is wired * (or with pins left open) still leaves ngspice a solvable circuit Rflt1 OUT1 0 1G Rflt2 IN1- 0 1G Rflt3 IN1+ 0 1G Rflt4 GND 0 1G Rflt5 IN2+ 0 1G Rflt6 IN2- 0 1G Rflt7 OUT2 0 1G Rflt8 VCC 0 1G .ends LM358 .subckt lm358_amp inp inn vcc vee out Rin inp inn 2Meg Rcm1 inp vee 100Meg Rcm2 inn vee 100Meg Iq vcc vee 350u G1 0 int inp inn 1m R1 int 0 100Meg C1 int 0 159p Bclip o 0 V = max(min(V(int), V(vcc)-1.5), V(vee)+0.02) Rout o out 50 .ends lm358_amp ","description":"The LM358 is a dual, single-supply operational amplifier. Both amplifiers share the VCC and GND pins and work from a single supply (3 V to 32 V in the real part), so no negative rail is needed. The inputs can sit at ground. The output swings down to about GND and up to about VCC - 1.5 V. Gain-bandwidth is about 1 MHz. Pins: 1 OUT1, 2 IN1-, 3 IN1+, 4 GND, 5 IN2+, 6 IN2-, 7 OUT2, 8 VCC.","public":true,"user_id":1953,"created_at":"2026-10-12T11:23:12.877Z","updated_at":"2026-10-12T11:23:12.877Z","official":true},{"id":1394,"name":"LM393","vertical_pins":4,"horizontal_pins":0,"pin_labels":{"left-3":"OUT1","left-2":"IN1-","left-1":"IN1+","left-0":"GND","right-3":"IN2+","right-2":"IN2-","right-1":"OUT2","right-0":"VCC","initial_checked":[]},"netlist":".subckt LM393 OUT1 IN1- IN1+ GND IN2+ IN2- OUT2 VCC * Dual open-collector comparator. OUT pulls to GND when IN+ < IN-; needs an external pull-up. X1 IN1+ IN1- GND OUT1 lm393_cmp X2 IN2+ IN2- GND OUT2 lm393_cmp Iq VCC GND 400u * every pin has a 1 Gohm path to ground, so a chip placed on the board before it is wired * (or with pins left open) still leaves ngspice a solvable circuit Rflt1 OUT1 0 1G Rflt2 IN1- 0 1G Rflt3 IN1+ 0 1G Rflt4 GND 0 1G Rflt5 IN2+ 0 1G Rflt6 IN2- 0 1G Rflt7 OUT2 0 1G Rflt8 VCC 0 1G .ends LM393 .subckt lm393_cmp inp inn vee out Rin inp inn 10Meg Rcm1 inp vee 100Meg Rcm2 inn vee 100Meg Bctl c 0 V = V(inn) - V(inp) S1 out vee c 0 swc .model swc sw(vt=0 vh=0.0005 ron=60 roff=1e10) .ends lm393_cmp ","description":"The LM393 is a dual voltage comparator with open-collector outputs. An output pulls to GND when its IN+ input is below its IN- input, and is released (floating) otherwise. Add a pull-up resistor from each output to a positive supply to get a logic high. Pins: 1 OUT1, 2 IN1-, 3 IN1+, 4 GND, 5 IN2+, 6 IN2-, 7 OUT2, 8 VCC.","public":true,"user_id":1953,"created_at":"2026-10-12T11:23:12.885Z","updated_at":"2026-10-12T11:23:12.885Z","official":true},{"id":1395,"name":"7805","vertical_pins":0,"horizontal_pins":3,"pin_labels":{"top-0":"","top-1":"","top-2":"","bottom-2":"IN","bottom-1":"GND","bottom-0":"OUT","initial_checked":[]},"netlist":".subckt 7805 IN GND OUT * 5 V fixed linear regulator (78xx family). Pin order is TO-220 pin 1..3: IN, GND, OUT. * Behaviour model of the datasheet figures (TI/onsemi 78xx, 25 C): * - regulates 5 V while IN is at least 2 V above OUT (dropout 2 V); below that OUT follows IN - 2 V * - current limit 2.2 A (typical peak output current) that folds back as IN - OUT rises, * down to about 0.7 A with OUT shorted from a 35 V input (short-circuit protection) * - quiescent (ground-pin) current about 5 mA; output current is drawn from IN * - the output only sources current, like the real part (it cannot pull OUT down) * - a 1 uF capacitor sits on OUT, as the datasheets recommend; it also gives the lab's start-from-zero * transient (.tran ... uic) a defined output at t = 0 * Not modelled: thermal shutdown, ripple rejection beyond ideal, line/load regulation of a few mV. Bset t GND V = min(5, max(V(IN,GND) - 2, 0)) Bpass IN OUT I = (V(t,GND) - V(OUT,GND) > 0) ? max(0.3, min(2.2, 2.2 - 0.06 * (V(IN,OUT) - 10))) * tanh((V(t,GND) - V(OUT,GND)) / 0.01 / max(0.3, min(2.2, 2.2 - 0.06 * (V(IN,OUT) - 10)))) : 0 Bq IN GND I = 5m * min(1, max(V(IN,GND), 0) / 2) Rt t GND 1Meg Rsnk OUT GND 1Meg Cout OUT GND 1u * every pin has a 1 Gohm path to ground, so a chip placed on the board before it is wired * (or with pins left open) still leaves ngspice a solvable circuit Rflt1 IN 0 1G Rflt2 GND 0 1G Rflt3 OUT 0 1G .ends 7805 ","description":"The 7805 is a fixed +5 V linear voltage regulator. The input must be at least about 2 V above the output (7 V or more) for regulation; below that the output follows the input, 2 V lower. It limits its output current to about 2.2 A, and less as the input-output difference grows (about 0.7 A with the output shorted from a 35 V input), so a short circuit is safe. It draws about 5 mA from IN for itself. Pins: 1 IN, 2 GND, 3 OUT.","public":true,"user_id":1953,"created_at":"2026-10-12T11:23:12.889Z","updated_at":"2026-10-12T11:23:12.889Z","official":true},{"id":1396,"name":"7812","vertical_pins":0,"horizontal_pins":3,"pin_labels":{"top-0":"","top-1":"","top-2":"","bottom-2":"IN","bottom-1":"GND","bottom-0":"OUT","initial_checked":[]},"netlist":".subckt 7812 IN GND OUT * 12 V fixed linear regulator (78xx family). Pin order is TO-220 pin 1..3: IN, GND, OUT. * Behaviour model of the datasheet figures (TI/onsemi 78xx, 25 C): * - regulates 12 V while IN is at least 2 V above OUT (dropout 2 V); below that OUT follows IN - 2 V * - current limit 2.2 A (typical peak output current) that folds back as IN - OUT rises, * down to about 0.7 A with OUT shorted from a 35 V input (short-circuit protection) * - quiescent (ground-pin) current about 5 mA; output current is drawn from IN * - the output only sources current, like the real part (it cannot pull OUT down) * - a 1 uF capacitor sits on OUT, as the datasheets recommend; it also gives the lab's start-from-zero * transient (.tran ... uic) a defined output at t = 0 * Not modelled: thermal shutdown, ripple rejection beyond ideal, line/load regulation of a few mV. Bset t GND V = min(12, max(V(IN,GND) - 2, 0)) Bpass IN OUT I = (V(t,GND) - V(OUT,GND) > 0) ? max(0.3, min(2.2, 2.2 - 0.06 * (V(IN,OUT) - 10))) * tanh((V(t,GND) - V(OUT,GND)) / 0.01 / max(0.3, min(2.2, 2.2 - 0.06 * (V(IN,OUT) - 10)))) : 0 Bq IN GND I = 5m * min(1, max(V(IN,GND), 0) / 2) Rt t GND 1Meg Rsnk OUT GND 1Meg Cout OUT GND 1u * every pin has a 1 Gohm path to ground, so a chip placed on the board before it is wired * (or with pins left open) still leaves ngspice a solvable circuit Rflt1 IN 0 1G Rflt2 GND 0 1G Rflt3 OUT 0 1G .ends 7812 ","description":"The 7812 is a fixed +12 V linear voltage regulator. The input must be at least about 2 V above the output (14 V or more) for regulation; below that the output follows the input, 2 V lower. It limits its output current to about 2.2 A, and less as the input-output difference grows (about 0.7 A with the output shorted from a 35 V input), so a short circuit is safe. It draws about 5 mA from IN for itself. Pins: 1 IN, 2 GND, 3 OUT.","public":true,"user_id":1953,"created_at":"2026-10-12T11:23:12.894Z","updated_at":"2026-10-12T11:23:12.894Z","official":true},{"id":1397,"name":"LM741","vertical_pins":4,"horizontal_pins":0,"pin_labels":{"left-3":"OFFSET1","left-2":"IN-","left-1":"IN+","left-0":"V-","right-3":"OFFSET2","right-2":"OUT","right-1":"V+","right-0":"NC","initial_checked":["right-2"]},"netlist":".subckt LM741 OFFSET1 IN- IN+ V- OFFSET2 OUT V+ NC * uA741 general-purpose op-amp. Pin order is DIP-8 pin 1..8. * Model: uA741 from the PSpice EVAL library (the same model as the existing LM741 IC, id 73), * with plain pin names. Run it from a split supply (for example V+ = +15 V, V- = -15 V); * the output swings to about 1-2 V from each rail. OFFSET1/OFFSET2 (offset null) and NC are * tied off with 1 Gohm so they may be left unconnected. c1 11 12 8.661E-12 c2 6 7 30.00E-12 dc OUT 53 dy de 54 OUT dy dlp 90 91 dx dln 92 90 dx dp V- V+ dx egnd 99 0 poly(2) (V+,0) (V-,0) 0 .5 .5 fb 7 99 poly(5) vb vc ve vlp vln 0 10.61E6 -1E3 1E3 10E6 -10E6 ga 6 0 11 12 188.5E-6 gcm 0 6 10 99 5.961E-9 iee 10 V- dc 15.16E-6 hlim 90 0 vlim 1K q1 11 IN- 13 qx q2 12 IN+ 14 qx r2 6 9 100.0E3 rc1 V+ 11 5.305E3 rc2 V+ 12 5.305E3 re1 13 10 1.836E3 re2 14 10 1.836E3 ree 10 99 13.19E6 ro1 8 OUT 50 ro2 7 99 100 rp V+ V- 18.16E3 vb 9 0 dc 0 vc V+ 53 dc 1 ve 54 V- dc 1 vlim 7 8 dc 0 vlp 91 0 dc 40 vln 0 92 dc 40 Rnul1 OFFSET1 V- 1G Rnul2 OFFSET2 V- 1G Rnc NC V- 1G .model dx D(Is=800.0E-18 Rs=1) .model dy D(Is=800.00E-18 Rs=1m Cjo=10p) .model qx NPN(Is=800.0E-18 Bf=93.75) * every pin has a 1 Gohm path to ground, so a chip placed on the board before it is wired * (or with pins left open) still leaves ngspice a solvable circuit Rflt1 OFFSET1 0 1G Rflt2 IN- 0 1G Rflt3 IN+ 0 1G Rflt4 V- 0 1G Rflt5 OFFSET2 0 1G Rflt6 OUT 0 1G Rflt7 V+ 0 1G Rflt8 NC 0 1G .ends LM741 ","description":"The 741 is the classic general-purpose operational amplifier used in most introductory electronics labs. Power it from a split supply, for example V+ = +15 V and V- = -15 V. The output swings to within about 1-2 V of each rail. Use it as an inverting or non-inverting amplifier, a voltage follower, a comparator, an integrator or a summing amplifier. Pins: 1 OFFSET1, 2 IN-, 3 IN+, 4 V-, 5 OFFSET2, 6 OUT, 7 V+, 8 NC. OFFSET1, OFFSET2 (offset null) and NC can be left unconnected.","public":true,"user_id":1953,"created_at":"2026-10-12T11:23:12.899Z","updated_at":"2026-10-12T11:23:12.899Z","official":true},{"id":1398,"name":"74LS00","vertical_pins":7,"horizontal_pins":0,"pin_labels":{"left-6":"1A","left-5":"1B","left-4":"1Y","left-3":"2A","left-2":"2B","left-1":"2Y","left-0":"GND","right-6":"3Y","right-5":"3A","right-4":"3B","right-3":"4Y","right-2":"4A","right-1":"4B","right-0":"VCC","initial_checked":[]},"netlist":".subckt 74LS00 1A 1B 1Y 2A 2B 2Y GND 3Y 3A 3B 4Y 4A 4B VCC * Quad 2-input NAND gate (74LS family), DIP-14. Pin order is physical pin 1..14: pin 7 GND, pin 14 VCC. * Logic is XSPICE digital (the same parts the official 555 uses). Inputs switch at TTL levels * (low below 0.8 V, high above 2.0 V) and an unconnected input reads high, as on a real LS part. * Each output pulls up to VCC through 470 ohm and an NPN pulls it down to GND. Rpu1A 1A VCC 20k Rpu1B 1B VCC 20k Rpu2A 2A VCC 20k Rpu2B 2B VCC 20k Rpu3A 3A VCC 20k Rpu3B 3B VCC 20k Rpu4A 4A VCC 20k Rpu4B 4B VCC 20k ain [1A 1B 2A 2B 3A 3B 4A 4B] [d1A d1B d2A d2B d3A d3B d4A d4B] ttl_in a1 [d1A d1B] q1 gate a2 [d2A d2B] q2 gate a3 [d3A d3B] q3 gate a4 [d4A d4B] q4 gate aout [q1 q2 q3 q4] [b1 b2 b3 b4] dac1 Rb1 b1 bb1 1k Q1 1Y bb1 GND N Ro1 1Y VCC 470 Rb2 b2 bb2 1k Q2 2Y bb2 GND N Ro2 2Y VCC 470 Rb3 b3 bb3 1k Q3 3Y bb3 GND N Ro3 3Y VCC 470 Rb4 b4 bb4 1k Q4 4Y bb4 GND N Ro4 4Y VCC 470 .model ttl_in adc_bridge(in_low = 0.8 in_high = 2.0) .model gate d_and(rise_delay = 10e-9 fall_delay = 10e-9 input_load = 0.5e-12) .model dac1 dac_bridge(out_low = 0.0 out_high = 1.0 out_undef = 0.5 + input_load = 5.0e-12 t_rise = 10e-9 t_fall = 10e-9) .model N NPN * every pin has a 1 Gohm path to ground, so a chip placed on the board before it is wired * (or with pins left open) still leaves ngspice a solvable circuit Rflt1 1A 0 1G Rflt2 1B 0 1G Rflt3 1Y 0 1G Rflt4 2A 0 1G Rflt5 2B 0 1G Rflt6 2Y 0 1G Rflt7 GND 0 1G Rflt8 3Y 0 1G Rflt9 3A 0 1G Rflt10 3B 0 1G Rflt11 4Y 0 1G Rflt12 4A 0 1G Rflt13 4B 0 1G Rflt14 VCC 0 1G .ends 74LS00 ","description":"The 74LS00 holds four 2-input NAND gates. Each output Y is LOW only when both inputs A and B are HIGH. Connect VCC (pin 14) to +5 V and GND (pin 7) to ground. An input below 0.8 V reads LOW and an input above 2.0 V reads HIGH. An unconnected input reads HIGH, as on a real 74LS chip. Pins: 1 1A, 2 1B, 3 1Y, 4 2A, 5 2B, 6 2Y, 7 GND, 8 3Y, 9 3A, 10 3B, 11 4Y, 12 4A, 13 4B, 14 VCC.","public":true,"user_id":1953,"created_at":"2026-10-12T11:23:12.904Z","updated_at":"2026-10-12T11:23:12.904Z","official":true},{"id":1399,"name":"74LS02","vertical_pins":7,"horizontal_pins":0,"pin_labels":{"left-6":"1Y","left-5":"1A","left-4":"1B","left-3":"2Y","left-2":"2A","left-1":"2B","left-0":"GND","right-6":"3A","right-5":"3B","right-4":"3Y","right-3":"4A","right-2":"4B","right-1":"4Y","right-0":"VCC","initial_checked":[]},"netlist":".subckt 74LS02 1Y 1A 1B 2Y 2A 2B GND 3A 3B 3Y 4A 4B 4Y VCC * Quad 2-input NOR gate (74LS family), DIP-14. Pin order is physical pin 1..14: pin 7 GND, pin 14 VCC. * Logic is XSPICE digital (the same parts the official 555 uses). Inputs switch at TTL levels * (low below 0.8 V, high above 2.0 V) and an unconnected input reads high, as on a real LS part. * Each output pulls up to VCC through 470 ohm and an NPN pulls it down to GND. Rpu1A 1A VCC 20k Rpu1B 1B VCC 20k Rpu2A 2A VCC 20k Rpu2B 2B VCC 20k Rpu3A 3A VCC 20k Rpu3B 3B VCC 20k Rpu4A 4A VCC 20k Rpu4B 4B VCC 20k ain [1A 1B 2A 2B 3A 3B 4A 4B] [d1A d1B d2A d2B d3A d3B d4A d4B] ttl_in a1 [d1A d1B] q1 gate a2 [d2A d2B] q2 gate a3 [d3A d3B] q3 gate a4 [d4A d4B] q4 gate aout [q1 q2 q3 q4] [b1 b2 b3 b4] dac1 Rb1 b1 bb1 1k Q1 1Y bb1 GND N Ro1 1Y VCC 470 Rb2 b2 bb2 1k Q2 2Y bb2 GND N Ro2 2Y VCC 470 Rb3 b3 bb3 1k Q3 3Y bb3 GND N Ro3 3Y VCC 470 Rb4 b4 bb4 1k Q4 4Y bb4 GND N Ro4 4Y VCC 470 .model ttl_in adc_bridge(in_low = 0.8 in_high = 2.0) .model gate d_or(rise_delay = 10e-9 fall_delay = 10e-9 input_load = 0.5e-12) .model dac1 dac_bridge(out_low = 0.0 out_high = 1.0 out_undef = 0.5 + input_load = 5.0e-12 t_rise = 10e-9 t_fall = 10e-9) .model N NPN * every pin has a 1 Gohm path to ground, so a chip placed on the board before it is wired * (or with pins left open) still leaves ngspice a solvable circuit Rflt1 1Y 0 1G Rflt2 1A 0 1G Rflt3 1B 0 1G Rflt4 2Y 0 1G Rflt5 2A 0 1G Rflt6 2B 0 1G Rflt7 GND 0 1G Rflt8 3A 0 1G Rflt9 3B 0 1G Rflt10 3Y 0 1G Rflt11 4A 0 1G Rflt12 4B 0 1G Rflt13 4Y 0 1G Rflt14 VCC 0 1G .ends 74LS02 ","description":"The 74LS02 holds four 2-input NOR gates. Each output Y is HIGH only when both inputs A and B are LOW. Connect VCC (pin 14) to +5 V and GND (pin 7) to ground. An input below 0.8 V reads LOW and an input above 2.0 V reads HIGH. An unconnected input reads HIGH, as on a real 74LS chip. Note the pinout differs from the 74LS00: on the 74LS02 each output comes before its inputs. Pins: 1 1Y, 2 1A, 3 1B, 4 2Y, 5 2A, 6 2B, 7 GND, 8 3A, 9 3B, 10 3Y, 11 4A, 12 4B, 13 4Y, 14 VCC.","public":true,"user_id":1953,"created_at":"2026-10-12T11:23:12.908Z","updated_at":"2026-10-12T11:23:12.908Z","official":true},{"id":1400,"name":"74LS04","vertical_pins":7,"horizontal_pins":0,"pin_labels":{"left-6":"1A","left-5":"1Y","left-4":"2A","left-3":"2Y","left-2":"3A","left-1":"3Y","left-0":"GND","right-6":"4Y","right-5":"4A","right-4":"5Y","right-3":"5A","right-2":"6Y","right-1":"6A","right-0":"VCC","initial_checked":[]},"netlist":".subckt 74LS04 1A 1Y 2A 2Y 3A 3Y GND 4Y 4A 5Y 5A 6Y 6A VCC * Hex inverter gate (74LS family), DIP-14. Pin order is physical pin 1..14: pin 7 GND, pin 14 VCC. * Logic is XSPICE digital (the same parts the official 555 uses). Inputs switch at TTL levels * (low below 0.8 V, high above 2.0 V) and an unconnected input reads high, as on a real LS part. * Each output pulls up to VCC through 470 ohm and an NPN pulls it down to GND. Rpu1A 1A VCC 20k Rpu2A 2A VCC 20k Rpu3A 3A VCC 20k Rpu4A 4A VCC 20k Rpu5A 5A VCC 20k Rpu6A 6A VCC 20k ain [1A 2A 3A 4A 5A 6A] [d1A d2A d3A d4A d5A d6A] ttl_in a1 d1A q1 gate a2 d2A q2 gate a3 d3A q3 gate a4 d4A q4 gate a5 d5A q5 gate a6 d6A q6 gate aout [q1 q2 q3 q4 q5 q6] [b1 b2 b3 b4 b5 b6] dac1 Rb1 b1 bb1 1k Q1 1Y bb1 GND N Ro1 1Y VCC 470 Rb2 b2 bb2 1k Q2 2Y bb2 GND N Ro2 2Y VCC 470 Rb3 b3 bb3 1k Q3 3Y bb3 GND N Ro3 3Y VCC 470 Rb4 b4 bb4 1k Q4 4Y bb4 GND N Ro4 4Y VCC 470 Rb5 b5 bb5 1k Q5 5Y bb5 GND N Ro5 5Y VCC 470 Rb6 b6 bb6 1k Q6 6Y bb6 GND N Ro6 6Y VCC 470 .model ttl_in adc_bridge(in_low = 0.8 in_high = 2.0) .model gate d_buffer(rise_delay = 10e-9 fall_delay = 10e-9 input_load = 0.5e-12) .model dac1 dac_bridge(out_low = 0.0 out_high = 1.0 out_undef = 0.5 + input_load = 5.0e-12 t_rise = 10e-9 t_fall = 10e-9) .model N NPN * every pin has a 1 Gohm path to ground, so a chip placed on the board before it is wired * (or with pins left open) still leaves ngspice a solvable circuit Rflt1 1A 0 1G Rflt2 1Y 0 1G Rflt3 2A 0 1G Rflt4 2Y 0 1G Rflt5 3A 0 1G Rflt6 3Y 0 1G Rflt7 GND 0 1G Rflt8 4Y 0 1G Rflt9 4A 0 1G Rflt10 5Y 0 1G Rflt11 5A 0 1G Rflt12 6Y 0 1G Rflt13 6A 0 1G Rflt14 VCC 0 1G .ends 74LS04 ","description":"The 74LS04 holds six inverters (NOT gates). Each output Y is the opposite of its input A. Connect VCC (pin 14) to +5 V and GND (pin 7) to ground. An input below 0.8 V reads LOW and an input above 2.0 V reads HIGH. An unconnected input reads HIGH, as on a real 74LS chip. Pins: 1 1A, 2 1Y, 3 2A, 4 2Y, 5 3A, 6 3Y, 7 GND, 8 4Y, 9 4A, 10 5Y, 11 5A, 12 6Y, 13 6A, 14 VCC.","public":true,"user_id":1953,"created_at":"2026-10-12T11:23:12.912Z","updated_at":"2026-10-12T11:23:12.912Z","official":true},{"id":1401,"name":"74LS08","vertical_pins":7,"horizontal_pins":0,"pin_labels":{"left-6":"1A","left-5":"1B","left-4":"1Y","left-3":"2A","left-2":"2B","left-1":"2Y","left-0":"GND","right-6":"3Y","right-5":"3A","right-4":"3B","right-3":"4Y","right-2":"4A","right-1":"4B","right-0":"VCC","initial_checked":[]},"netlist":".subckt 74LS08 1A 1B 1Y 2A 2B 2Y GND 3Y 3A 3B 4Y 4A 4B VCC * Quad 2-input AND gate (74LS family), DIP-14. Pin order is physical pin 1..14: pin 7 GND, pin 14 VCC. * Logic is XSPICE digital (the same parts the official 555 uses). Inputs switch at TTL levels * (low below 0.8 V, high above 2.0 V) and an unconnected input reads high, as on a real LS part. * Each output pulls up to VCC through 470 ohm and an NPN pulls it down to GND. Rpu1A 1A VCC 20k Rpu1B 1B VCC 20k Rpu2A 2A VCC 20k Rpu2B 2B VCC 20k Rpu3A 3A VCC 20k Rpu3B 3B VCC 20k Rpu4A 4A VCC 20k Rpu4B 4B VCC 20k ain [1A 1B 2A 2B 3A 3B 4A 4B] [d1A d1B d2A d2B d3A d3B d4A d4B] ttl_in a1 [d1A d1B] q1 gate a2 [d2A d2B] q2 gate a3 [d3A d3B] q3 gate a4 [d4A d4B] q4 gate aout [q1 q2 q3 q4] [b1 b2 b3 b4] dac1 Rb1 b1 bb1 1k Q1 1Y bb1 GND N Ro1 1Y VCC 470 Rb2 b2 bb2 1k Q2 2Y bb2 GND N Ro2 2Y VCC 470 Rb3 b3 bb3 1k Q3 3Y bb3 GND N Ro3 3Y VCC 470 Rb4 b4 bb4 1k Q4 4Y bb4 GND N Ro4 4Y VCC 470 .model ttl_in adc_bridge(in_low = 0.8 in_high = 2.0) .model gate d_nand(rise_delay = 10e-9 fall_delay = 10e-9 input_load = 0.5e-12) .model dac1 dac_bridge(out_low = 0.0 out_high = 1.0 out_undef = 0.5 + input_load = 5.0e-12 t_rise = 10e-9 t_fall = 10e-9) .model N NPN * every pin has a 1 Gohm path to ground, so a chip placed on the board before it is wired * (or with pins left open) still leaves ngspice a solvable circuit Rflt1 1A 0 1G Rflt2 1B 0 1G Rflt3 1Y 0 1G Rflt4 2A 0 1G Rflt5 2B 0 1G Rflt6 2Y 0 1G Rflt7 GND 0 1G Rflt8 3Y 0 1G Rflt9 3A 0 1G Rflt10 3B 0 1G Rflt11 4Y 0 1G Rflt12 4A 0 1G Rflt13 4B 0 1G Rflt14 VCC 0 1G .ends 74LS08 ","description":"The 74LS08 holds four 2-input AND gates. Each output Y is HIGH only when both inputs A and B are HIGH. Connect VCC (pin 14) to +5 V and GND (pin 7) to ground. An input below 0.8 V reads LOW and an input above 2.0 V reads HIGH. An unconnected input reads HIGH, as on a real 74LS chip. Pins: 1 1A, 2 1B, 3 1Y, 4 2A, 5 2B, 6 2Y, 7 GND, 8 3Y, 9 3A, 10 3B, 11 4Y, 12 4A, 13 4B, 14 VCC.","public":true,"user_id":1953,"created_at":"2026-10-12T11:23:12.916Z","updated_at":"2026-10-12T11:23:12.916Z","official":true},{"id":1402,"name":"74LS32","vertical_pins":7,"horizontal_pins":0,"pin_labels":{"left-6":"1A","left-5":"1B","left-4":"1Y","left-3":"2A","left-2":"2B","left-1":"2Y","left-0":"GND","right-6":"3Y","right-5":"3A","right-4":"3B","right-3":"4Y","right-2":"4A","right-1":"4B","right-0":"VCC","initial_checked":[]},"netlist":".subckt 74LS32 1A 1B 1Y 2A 2B 2Y GND 3Y 3A 3B 4Y 4A 4B VCC * Quad 2-input OR gate (74LS family), DIP-14. Pin order is physical pin 1..14: pin 7 GND, pin 14 VCC. * Logic is XSPICE digital (the same parts the official 555 uses). Inputs switch at TTL levels * (low below 0.8 V, high above 2.0 V) and an unconnected input reads high, as on a real LS part. * Each output pulls up to VCC through 470 ohm and an NPN pulls it down to GND. Rpu1A 1A VCC 20k Rpu1B 1B VCC 20k Rpu2A 2A VCC 20k Rpu2B 2B VCC 20k Rpu3A 3A VCC 20k Rpu3B 3B VCC 20k Rpu4A 4A VCC 20k Rpu4B 4B VCC 20k ain [1A 1B 2A 2B 3A 3B 4A 4B] [d1A d1B d2A d2B d3A d3B d4A d4B] ttl_in a1 [d1A d1B] q1 gate a2 [d2A d2B] q2 gate a3 [d3A d3B] q3 gate a4 [d4A d4B] q4 gate aout [q1 q2 q3 q4] [b1 b2 b3 b4] dac1 Rb1 b1 bb1 1k Q1 1Y bb1 GND N Ro1 1Y VCC 470 Rb2 b2 bb2 1k Q2 2Y bb2 GND N Ro2 2Y VCC 470 Rb3 b3 bb3 1k Q3 3Y bb3 GND N Ro3 3Y VCC 470 Rb4 b4 bb4 1k Q4 4Y bb4 GND N Ro4 4Y VCC 470 .model ttl_in adc_bridge(in_low = 0.8 in_high = 2.0) .model gate d_nor(rise_delay = 10e-9 fall_delay = 10e-9 input_load = 0.5e-12) .model dac1 dac_bridge(out_low = 0.0 out_high = 1.0 out_undef = 0.5 + input_load = 5.0e-12 t_rise = 10e-9 t_fall = 10e-9) .model N NPN * every pin has a 1 Gohm path to ground, so a chip placed on the board before it is wired * (or with pins left open) still leaves ngspice a solvable circuit Rflt1 1A 0 1G Rflt2 1B 0 1G Rflt3 1Y 0 1G Rflt4 2A 0 1G Rflt5 2B 0 1G Rflt6 2Y 0 1G Rflt7 GND 0 1G Rflt8 3Y 0 1G Rflt9 3A 0 1G Rflt10 3B 0 1G Rflt11 4Y 0 1G Rflt12 4A 0 1G Rflt13 4B 0 1G Rflt14 VCC 0 1G .ends 74LS32 ","description":"The 74LS32 holds four 2-input OR gates. Each output Y is HIGH when input A or input B (or both) is HIGH. Connect VCC (pin 14) to +5 V and GND (pin 7) to ground. An input below 0.8 V reads LOW and an input above 2.0 V reads HIGH. An unconnected input reads HIGH, as on a real 74LS chip. Pins: 1 1A, 2 1B, 3 1Y, 4 2A, 5 2B, 6 2Y, 7 GND, 8 3Y, 9 3A, 10 3B, 11 4Y, 12 4A, 13 4B, 14 VCC.","public":true,"user_id":1953,"created_at":"2026-10-12T11:23:12.921Z","updated_at":"2026-10-12T11:23:12.921Z","official":true},{"id":1403,"name":"74LS86","vertical_pins":7,"horizontal_pins":0,"pin_labels":{"left-6":"1A","left-5":"1B","left-4":"1Y","left-3":"2A","left-2":"2B","left-1":"2Y","left-0":"GND","right-6":"3Y","right-5":"3A","right-4":"3B","right-3":"4Y","right-2":"4A","right-1":"4B","right-0":"VCC","initial_checked":[]},"netlist":".subckt 74LS86 1A 1B 1Y 2A 2B 2Y GND 3Y 3A 3B 4Y 4A 4B VCC * Quad 2-input XOR gate (74LS family), DIP-14. Pin order is physical pin 1..14: pin 7 GND, pin 14 VCC. * Logic is XSPICE digital (the same parts the official 555 uses). Inputs switch at TTL levels * (low below 0.8 V, high above 2.0 V) and an unconnected input reads high, as on a real LS part. * Each output pulls up to VCC through 470 ohm and an NPN pulls it down to GND. Rpu1A 1A VCC 20k Rpu1B 1B VCC 20k Rpu2A 2A VCC 20k Rpu2B 2B VCC 20k Rpu3A 3A VCC 20k Rpu3B 3B VCC 20k Rpu4A 4A VCC 20k Rpu4B 4B VCC 20k ain [1A 1B 2A 2B 3A 3B 4A 4B] [d1A d1B d2A d2B d3A d3B d4A d4B] ttl_in a1 [d1A d1B] q1 gate a2 [d2A d2B] q2 gate a3 [d3A d3B] q3 gate a4 [d4A d4B] q4 gate aout [q1 q2 q3 q4] [b1 b2 b3 b4] dac1 Rb1 b1 bb1 1k Q1 1Y bb1 GND N Ro1 1Y VCC 470 Rb2 b2 bb2 1k Q2 2Y bb2 GND N Ro2 2Y VCC 470 Rb3 b3 bb3 1k Q3 3Y bb3 GND N Ro3 3Y VCC 470 Rb4 b4 bb4 1k Q4 4Y bb4 GND N Ro4 4Y VCC 470 .model ttl_in adc_bridge(in_low = 0.8 in_high = 2.0) .model gate d_xnor(rise_delay = 10e-9 fall_delay = 10e-9 input_load = 0.5e-12) .model dac1 dac_bridge(out_low = 0.0 out_high = 1.0 out_undef = 0.5 + input_load = 5.0e-12 t_rise = 10e-9 t_fall = 10e-9) .model N NPN * every pin has a 1 Gohm path to ground, so a chip placed on the board before it is wired * (or with pins left open) still leaves ngspice a solvable circuit Rflt1 1A 0 1G Rflt2 1B 0 1G Rflt3 1Y 0 1G Rflt4 2A 0 1G Rflt5 2B 0 1G Rflt6 2Y 0 1G Rflt7 GND 0 1G Rflt8 3Y 0 1G Rflt9 3A 0 1G Rflt10 3B 0 1G Rflt11 4Y 0 1G Rflt12 4A 0 1G Rflt13 4B 0 1G Rflt14 VCC 0 1G .ends 74LS86 ","description":"The 74LS86 holds four 2-input XOR (exclusive-OR) gates. Each output Y is HIGH when exactly one of inputs A and B is HIGH, and LOW when both are the same. Connect VCC (pin 14) to +5 V and GND (pin 7) to ground. An input below 0.8 V reads LOW and an input above 2.0 V reads HIGH. An unconnected input reads HIGH, as on a real 74LS chip. Pins: 1 1A, 2 1B, 3 1Y, 4 2A, 5 2B, 6 2Y, 7 GND, 8 3Y, 9 3A, 10 3B, 11 4Y, 12 4A, 13 4B, 14 VCC.","public":true,"user_id":1953,"created_at":"2026-10-12T11:23:12.927Z","updated_at":"2026-10-12T11:23:12.927Z","official":true},{"id":4,"name":"LM317","vertical_pins":0,"horizontal_pins":3,"pin_labels":{"top-0":"","top-1":"","top-2":"","bottom-2":"adj","bottom-1":"out","bottom-0":"in","initial_checked":[]},"netlist":".subckt LM317 adj out in * LM317 adjustable positive linear regulator. Ports are in the order the lab binds this IC's bottom row: * ADJ, OUT, IN, which is also the TO-220 pin order 1, 2, 3. * Behaviour model of the datasheet figures (TI LM317, 25 C): * - holds OUT 1.25 V above ADJ: with R1 from OUT to ADJ and R2 from ADJ to ground, * Vout = 1.25 V * (1 + R2/R1) + 50 uA * R2 * - about 50 uA flows out of ADJ, drawn from IN (none when IN is reversed) * - dropout 2 V: below that OUT follows IN - 2 V * - current limit 2.2 A that folds back as IN - OUT rises (about 0.7 A at 35 V across the part) * - the output only sources current; all output current is drawn from IN * - a 1 uF capacitor on OUT (to ground, like the datasheet's output capacitor) gives the lab's start-from-zero transient (.tran ... uic) a defined * output at t = 0 * Not modelled: thermal shutdown, the 3.5 mA minimum load, ripple rejection beyond ideal. Bset t 0 V = max(min(V(adj) + 1.25, V(in) - 2), 0) Bpass in out I = (V(t) - V(out) > 0) ? max(0.3, min(2.2, 2.2 - 0.06 * (V(in,out) - 10))) * tanh((V(t) - V(out)) / 0.01 / max(0.3, min(2.2, 2.2 - 0.06 * (V(in,out) - 10)))) : 0 Badj in adj I = 50u * min(1, max(V(in,adj), 0) / 2) Rt t 0 1Meg Rsnk out adj 1Meg Cout out 0 1u * every pin has a 1 Gohm path to ground, so a chip placed on the board before it is wired * (or with pins left open) still leaves ngspice a solvable circuit Rflt1 adj 0 1G Rflt2 out 0 1G Rflt3 in 0 1G .ends LM317 ","description":"The LM317 is an adjustable positive voltage regulator. It holds OUT 1.25 V above ADJ, so two resistors set the output: R1 from OUT to ADJ (240 ohm is typical) and R2 from ADJ to ground give Vout = 1.25 V x (1 + R2 / R1). For example, 240 ohm and 720 ohm give about 5 V. The input must be at least about 2 V above the output. It limits its output current to about 2.2 A, less as the input-output difference grows, so a short circuit is safe. A resistor from OUT to ADJ with the load on ADJ turns it into a constant-current source: I = 1.25 V / R. Pins: 1 ADJ, 2 OUT, 3 IN.","public":true,"user_id":1953,"created_at":"2025-04-01T06:52:09.037Z","updated_at":"2026-10-12T11:23:12.933Z","official":true},{"id":1,"name":"555","vertical_pins":4,"horizontal_pins":0,"pin_labels":{"right-0":"VCC","right-1":"DISCH","right-2":"THRSH","right-3":"CONT","left-0":"RESET","left-1":"OUT","left-2":"TRIGGER","left-3":"GND","initial_checked":["right-2"]},"netlist":".subckt 555 GND TRIGGER OUT RESET CONT THRSH DISCH VCC * Version 2 using generic OpAmp model from the forum. * Now supports output voltage set by Vcc Pin. * This is mostly a timing model and may not be DC accurate in all cases. * credit: https://sourceforge.net/p/ngspice/discussion/ngspice-tips/thread/f535c0f1b9/ * Pin mapping: * GND * TRIGGER * OUT * RESET * CONT * THRSH * DISCH * VCC R1 VCC CONT 5000 R2 CONT 10 5000 R3 10 GND 5000 X1 THRSH CONT VCC 0 11 genopa1 ; the reset comparator X2 10 TRIGGER VCC 0 12 genopa1 ; the set comparator * R S R S abridge [11 12] [22 21] adc_buff ; bridge from comparators to set/reset controls a0 z1 pulldown1 ; pull-down for unused clock and data * data clock set reset q qbar a1 z1 z1 21 25 23 24 flop1 ; the flip-flop abridge1 [24] [13] dac1 ; bridge qbar to discharge timing cap, turn on Q1 abridge2 [24] [26] dac1 ; bridge qbar to pseudo tristate driver Q1 DISCH 13 GND N ; the discharge transistor * Active low master reset from pin RESET abridge3 [RESET] [30] adc_buff a2 30 31 inv1 a3 [22 31] 25 or1 ; Reset when external reset is asserted or comparator trips * Make the Q output of the flip-flop drive to VCC when driven R4 OUT VCC 100 Q2 OUT 26 0 N * Models .model adc_buff adc_bridge(in_low = 0.7 in_high = 3.0) .model flop1 d_dff(clk_delay = 13.0e-9 set_delay = 25.0e-9 + reset_delay = 27.0e-9 ic = 0 rise_delay = 10.0e-9 + fall_delay = 3e-9) .model pulldown1 d_pulldown(load = 20.0e-12) .model dac1 dac_bridge(out_low = 0.1 out_high = 1.0 out_undef = 2.2 + input_load = 5.0e-12 t_rise = 50e-9 + t_fall = 20e-9) .model N NPN .model inv1 d_inverter(rise_delay = 0.5e-9 fall_delay = 0.3e-9 + input_load = 0.5e-12) .model or1 d_or(rise_delay = 0.5e-9 fall_delay = 0.3e-9 + input_load = 0.5e-12) * every pin has a 1 Gohm path to ground, so a 555 placed on the board before it is wired * (or with pins left open) still leaves ngspice a solvable circuit Rflt1 GND 0 1G Rflt2 TRIGGER 0 1G Rflt3 OUT 0 1G Rflt4 RESET 0 1G Rflt5 CONT 0 1G Rflt6 THRSH 0 1G Rflt7 DISCH 0 1G Rflt8 VCC 0 1G .ends 555 * Generic OpAmp model .subckt genopa1 in+ in- vcc vee out params: POLE=20 GAIN=20k VOFFSET=5m ROUT=10 RIN=10Meg Rin in+ in+ {RIN} Voff in+ inoff dc {VOFFSET} G10 0 int inoff in- 100u R1 int 0 {GAIN/100u} C1 int 0 {1/(6.28*(GAIN/100u)*POLE)} Eout 2 0 int 0 1 Rout 2 out {ROUT} Elow 3 0 vee 0 1 Ehigh 8 0 vcc 0 1 Dlow 3 int Dlimit Dhigh int 8 Dlimit .model Dlimit D N=0.01 .ends .end ","description":"The 555 timer is a versatile integrated circuit capable of operating in three distinct modes: 1. Astable Mode (Free-Running Oscillator) The 555 continuously generates square wave pulses without requiring external trigger pulses. The output oscillates between HIGH and LOW states indefinitely. The frequency and duty cycle are determined by external resistors (R1, R2) and a capacitor (C). This mode is ideal for generating clock signals, tone generators, and LED flashers. 2. Monostable Mode (One-Shot Timer) The 555 produces a single output pulse of a specific duration when triggered by an input pulse. After the pulse completes, the circuit returns to its stable LOW state and waits for the next trigger. This mode is perfect for precision timing applications and pulse generation. 3. Bistable Mode (Flip-Flop) The 555 acts as a latch, switching states based on separate SET and RESET inputs. The output remains in its current state until commanded to change, making it useful for toggle switches and latching circuits.","public":true,"user_id":1953,"created_at":"2025-03-29T15:05:00.797Z","updated_at":"2026-10-12T12:34:29.161Z","official":true}],"show_ic_creator":false,"is_breadboard_lab":false}